The present invention generally relates to bondpad arrays, and more specifically relates to a bondpad array which is vertically staggered, thereby providing that die size can be reduced.
One of the driving factors in development of new process technologies is the reduction of die size, allowing more die to be manufactured in a given surface area. Increases in semiconductor device capabilities, integration, and technology result in increasing chip functionality. This often results in a device which includes a large number of Input/Output (I/O) pins to the device. The interface between the silicon device and the package typically consists of a metallic bond pad (BP) on the silicon chip to which a bond wire conductor is attached. This wire conductor is attached to the device package, which serves as the device interface to the electrical environment outside the package. This connection is usually made at the top metal layer of the chip.
The bond wire-to-bond-pad region (often referred to as the “ball bond”) has a physical size minimum beyond which the device becomes physically unmanufacturable. At a certain point, the size of the die becomes constrained by the number of I/O pins of the device. The area required for the internal circuitry of the device is smaller than the area around the perimeter of the circuitry required for a high number of I/O pins, bond pads, and their associated bond wires.
The current methodology for minimizing the space required for I/O connections involves horizontally staggering the bond pads. This technique significantly reduces the space required along the side of the device for I/O connections. As illustrated in FIG. 1, bond wires 10 terminate at ball bonds 12, and the ball bonds 12 are bonded to bond pads 14 which are located on a silicon substrate 15 of the device 16. As shown, even when bond pads 14 are horizontally staggered, all the bond pad connections are made at the top metal layer 18 of the device 16 (i.e., all the connections are made on the same plane 20). Certain horizontal minimum-space rules are required between adjacent bond pads 14 in order to prevent electrical contact between adjacent ball bonds 12.
While horizontally staggering the bond pads on a device reduces the space required along the side of the device for I/O connections, it is desirable to devise ways to even further reduce the space which is required along the side of a device for I/O connections.
Flip-Chip bond pad methodology places the bond pad on the surface of the die covering the active area of the circuitry. This eliminates the need for space allotment along the edge of the die for I/O purposes, however there are many drawbacks to this technique. Flip-Chip methodology requires additional processing steps adding much cost and complexity to manufacturing. It also severely impacts failure-analysis and debugging, resulting in much costlier and higher cycle times for yield improvement efforts.